1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor, more particular to a semiconductor device and a manufacturing method therefor concerning increase in a capacitance of a capacitor.
2. Description of the Background Art
A three dimensional structure has come to be adopted for DRAM (dynamic random access memory) capacitors in order to secure the necessary capacitance in accordance with the scaling down of the design rule. Here, in reference to FIG. 13, a cross sectional structure of a cylindrical capacitor having a three dimensional structure adopted in a DRAM according to a prior art will be described. A bit line 102 and a storage node contact 103 are embedded into an interlayer insulating film 101.
A storage node interlayer insulating film 104 made of TEOS (Tetra Etyle Ortho Silicate) or the like is formed on interlayer insulating film 101, and a contact hole 104b which reaches to storage node contact 103 is provided on a predetermined region of this storage node interlayer insulating film 104.
A storage node (lower electrode) 108 made of a polysilicon, or the like, of which the surface has a rough state, is provided on the inner side wall of this contact hole 104b so as to form a cylinder type, and storage node contact 103 and storage node 108 are electrically connected in a bottom surface of contact hole 104b. In addition, a cell plate (upper electrode) 111 made of TiN or the like is embedded into the contact hole so as to cover the surface of storage node 108 with a dielectric film (not shown) interposed. The above described storage node 108, the dielectric film and cell plate 111 form a stacked-type cylindrical capacitor (concave type) of a DRAM.
An interlayer insulating film 112 is provided so as to cover cell plate 111 and storage node interlayer insulating film 104, and an aluminum wire 116 provided on the top surface of this interlayer insulating film 112 and cell plate 111 are electrically connected through a contact plug 114 which is embedded into a contact hole 112a provided on interlayer insulating film 112.
In addition, bit line 102 provided on another region is electrically connected to aluminum wire 116 through a contact plug 115 which is embedded into a contact hole 104a penetrating interlayer insulating film 101, storage node interlayer insulating film 104 and interlayer insulating film 112.
Here, in the case that the above described stacked-type cylindrical capacitor according to the prior art is taken into consideration, the process aspect ratio of the storage node (SN) for charge storage becomes extreme. On the other hand, at the time of dry etching of the storage node (SN), a protrusion of a tapered shape is formed at the bottom of the cylinder and; therefore, there is a problem that a sufficient opening diameter cannot be obtained at the bottom of the cylinder and the capacitance of the capacitor cannot be sufficiently secured.
In addition, in the case that the height of the cylinder is increased in order in order to secure the capacitance of the capacitor, not only the aspect ratio of the SN process but also the aspect ratio to contact hole opening for a wire provided in a subsequent step become too large and, therefore, become a factor that lowers the process yield.
An object of the present invention is to solve the above described problems and to provide a semiconductor device and a manufacturing method therefor wherein an easy process can be adopted and the increase in the capacitance of the capacitor is made possible.
In a manufacturing method for a semiconductor device according to the present invention, a manufacturing method for a semiconductor device having a memory cell region and a peripheral region, wherein the memory cell region includes a lower electrode electrically connected to a predetermined first connection region and an upper electrode provided to the lower electrode with a dielectric film interposed, includes the steps of: forming a first interlayer insulating film on the first connection region; forming a second interlayer insulating film, of which a wet etching ratio with respect to a predetermined wet etchant is greater than that of the first interlayer insulating film, on the first interlayer insulating film (4); forming a first contact hole which penetrates the first interlayer insulating film and the second interlayer insulating film to reach up to the first connection region in the memory cell region, and which is provided in a connection region between the first interlayer insulating film and the second interlayer insulating film such that an inner diameter of the first interlayer insulating film becomes greater than that of the second interlayer insulating film; forming the lower electrode in a cylindrical form along an inner surface of the first contact hole; removing only the second interlayer insulating film in the memory cell region; and interposing the dielectric film with respect to the lower electrode to embed the dielectric film into an inner peripheral surface of the lower electrode, and forming the upper electrode so as to surround an outer peripheral surface of the lower electrode.
By adopting this manufacturing method, it is made possible to form the large inner diameter of the first contact hole formed on the first interlayer insulating film which is positioned in a lower layer utilizing a wet etching ratio of a wet etchant. As a result of this, it is made possible to avoid the difficulty of forming contact hole, due to a large aspect ratio, at the time of forming contact hole in conventional dry etching.
In addition, in the lower edge portion region of the first contact hole, it is made possible to increase the capacitance of the capacitor formed of a lower electrode, a dielectric film and an upper electrode in this region and it becomes possible to increase the refresh characteristics of a DRAM in which this capacitor is applied.
Furthermore, since the wet etching ratios of wet etchants for the first interlayer insulating film and for the second interlayer insulating film are positively made different, the formation of a cylindrical-type capacitor that utilizes the outer peripheral surface region in the cylindrical portion of the lower electrode becomes possible by adopting the step wherein the second interlayer insulating film alone can be easily removed and, in addition, it becomes possible to increase the capacitance of the capacitor.
In addition, the above described manufacturing method for the semiconductor device preferably includes the steps of: forming a third interlayer insulating film which covers the upper electrode and the second interlayer insulating film; forming a second connection region in advance in a position lower than the first interlayer insulating film in the peripheral region; forming a contact hole which reaches up to the second connection region after the formation of the first interlayer insulating film, and forming a first contact plug within this contact hole; and creating a contact hole which reaches up to the first contact plug and which penetrates the second interlayer insulating film and the third interlayer insulating film after the formation of the third interlayer insulating film, and forming a second contact plug within this contact hole.
By adopting this manufacturing method, the steps are adopted wherein the first contact plug is formed before formation of the second interlayer insulating film and the second contact plug is formed after the formation of the second interlayer insulating film and, therefore, formation according to a low aspect ratio becomes possible in the formation of the first contact plug and in the formation of the second contact plug.
In addition, the above described manufacturing method for a semiconductor device preferably includes a step of forming an etching stopper film between the first interlayer insulating film and the second interlayer insulating film.
By adopting this manufacturing method, the etching rate difference in wet etching in the border between the first interlayer insulating film and the second interlayer insulating film becomes clearer and, therefore, control for removing the second interlayer insulating film alone through etching is made easier.
Next, in a semiconductor device according to the present invention, a semiconductor device having a memory cell region and a peripheral region, wherein the memory cell region includes a lower electrode electrically connected to a predetermined first connection region and an upper electrode provided to the lower electrode with a dielectric film interposed, includes: a first interlayer insulating film provided on the first connection region in the memory cell region; a second interlayer insulating film provided on the first interlayer insulating film in the peripheral region; a first contact hole which reaches up to the first connection region and which penetrates the first interlayer insulating film; the lower electrode provided in a cylindrical form so as to extend along an inner surface of the first contact hole and to upwardly protrude from an upper surface of the first interlayer insulating film; and the upper electrode which interposes the dielectric film with respect to the lower electrode to embed the dielectric film into an inner peripheral surface of the lower electrode and which is provided so as to surround an outer peripheral surface of the lower electrode, wherein an outer diameter of the lower electrode positioned within the first interlayer insulating film is provided so as to become greater than that of the lower electrode coming into contact with the upper electrode in a boundary region between the first interlayer insulating film and the upper electrode.
By adopting this structure, the inner diameter of the first contact hole is made large in a region of the first interlayer insulating film of this first contact hole and, therefore, it becomes possible to increase the capacitance of the capacitor formed of a lower electrode, a dielectric film and an upper electrode in this region. As a result of this, it becomes possible to increase the refresh characteristics of a DRAM in which such a capacitor is applied.
In addition, a cylindrical-type capacitor which utilizes the outer peripheral surface region of a cylindrical portion of a lower electrode is implemented and, thereby, it becomes possible to further increase the capacitance of the capacitor.
In addition, the above described semiconductor device preferably includes: a third interlayer insulating film which covers the upper electrode and the second interlayer insulating film; a second connection region in a position lower than the first interlayer insulating film of the peripheral region; and a second contact hole which reaches to the second connection region and which penetrates the first interlayer insulating film, the second interlayer insulating film and the third connection region, wherein a first contact plug is provided in a region positioned in the first interlayer insulating film of the second contact hole and a second contact plug is provided in a region positioned in the second interlayer insulating film and in the third interlayer insulating film of the second contact hole, wherein the second contact hole is provided so that the inner diameter in the first interlayer insulating film is greater than the inner diameter in the second interlayer insulating film in a connection region between the first interlayer insulating film and the second interlayer insulating film.
By adopting this structure, it becomes possible to form a contact, without fail, between a wire contact a peripheral region and the second connection region that is located in the lower layer.
In addition, in the above described semiconductor device, an etching stopper film is preferably further provided between the first interlayer insulating film and the second interlayer insulating film.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.